Improvements in memory device applications result in larger cell arrays and faster memory access requirements. For example, dynamic random access memories (DRAMs) use an array of memory cells, sense amplifiers, drivers and support electronics to manage data read, data write and cell refresh operations. The memory cells are generally miniature capacitors which vary in stored charge according to the voltage written to the cell. Since each memory cell has leakage losses, each cell must be refreshed periodically to prevent loss of the information in each cell. This is called a "writeback" operation and is performed by periodically reading each cell and refreshing the cell by internally writing a logic one to the cells storing a one. Additionally, each cell is rewritten upon a read instruction, since the reads are destructive without the immediate rewrite.
Static memories (SRAMs) include an array of active memory cells which maintain a programmed logic state without the need for refresh. Increasingly larger memory cell arrays add to the latency of cell read and write operations.
Therefore, there is a need in the art for a system for faster memory cell access and refresh. The system should be implemented with the fewest number of modifications to avoid complications to the chip topology and increased power dissipation.